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专利名称：Method and apparatus for at-speed testing
of digital circuits
发明人：Janusz Rajski,Abu Hassan,Robert
Thompson,Nagesh Tamarapalli
申请号：US10301127申请日：20021120公开号：US06966021B2公开日：20051115
专利附图：
摘要：A scheme for multi-frequency at-speed logic Built-In Self Test (BIST) is
provided. This scheme allows at-speed testing of very high frequency integrated circuits
controlled by a clock signal generated externally or on-chip. The scheme is also
applicable to testing of circuits with multiple clock domains which can be either the samefrequency or different frequency. Scanable memory elements of the digital circuit areconnected to define plurality of scan chains. The loading and unloading of scan chains isseparated from the at-speed testing of the logic between the respective domains andmay be done at a faster or slower frequency than the at-speed testing. The BIST
controller, Pseudo-Random Pattern Generator (PRPG) and Multi-input Signature Register(MISR) work at slower frequency than the fastest clock domain. After loading of a newtest pattern, a clock suppression circuit allows a scan enable signal to propagate formore that one clock cycle before multiple capture clock is applied. This feature relaxesthe speed and skew constraints on scan enable signal design. Only the capture cycle isperformed at the corresponding system timing. A programmable capture window makesit possible to test every intra- and inter-domain at-speed without the negative impact ofclock skew between clock domains.
申请人：Janusz Rajski,Abu Hassan,Robert Thompson,Nagesh Tamarapalli
地址：6502 Horton Rd. West Linn OR 97068 US,3585 Sandpebble Dr. #600 San Jose CA95136 US,9270 SW. Stone Dr. Tualatin OR 97062 US,29290 SW. Parkway Ct. #93 WilsonvilleOR 97070 US
国籍：US,US,US,US
代理机构：Klarquist Sparkman, LLP
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